1. Field of the Invention
The invention related to a memory structure and a fabricating method thereof. More particularly, the invention relates to a memory structure having a plurality of charge storage units which is physically separated and a fabricating method thereof.
2. Description of Related Art
A memory is a semiconductor device designed to store information or data. As micro-processors become more functional, the programs and operations performed by software increase as well. Thus, the demand for high capacity memory becomes higher. In various memory products, non-volatile memory such as electrically erasable programmable read only memory (EEPROM) allows multiple data programming, reading, and erasing operations. Here, the data stored therein are saved even after the memory has been disconnected. According to the advantages mentioned above, EEPROM has become a memory widely adopted in personal computers and electronic apparatuses.
In a typical EEPROM, a floating gate and a control gate are fabricated using doped polysilicon. When the memory is being programmed, electrons injected into the floating gate then distribute evenly in the entire polysilicon floating gate. However, when defects are present in a tunnel oxide layer disposed under the polysilicon floating gate, current leakage of devices then occurs easily, thereby affecting the reliability of devices.
As a result, in order to prevent current leakage in EEPROM, a conventional method is to replace the polysilicon floating gate with a gate structure having a non-conductive charge storage layer. Another advantage of replacing the polysilicon floating gate with the charge storage layer is that when the device is being programmed, electrons are only stored locally in the charge storage layer above a source or a drain. Therefore, a source region and a control gate at one end of a stacked gate are applied with a voltage respectively during the programming so as to generate electrons with Gaussian distribution in the charge storage layer close to the source region. Moreover, a drain region at one end of the stacked gate and the control gate are also applied with a voltage respectively to generate electrons with Gaussian distribution in the charge storage layer close to the drain region. Consequently, by changing the voltage applied in the control gate and the source/drain regions at the two sides thereof, two groups of electrons with Gaussian distribution, one group of electrons with Gaussian distribution, or no electrons can be present in a single charge storage layer. Accordingly, the flash memory replacing the floating gate with the charge storage layer can be written into a single memory cell in four states and is a flash memory with a 2 bits/cell storage.
Nevertheless, along with the increasing integrity of the semiconductor device, the dimension of the non-volatile memory is miniaturized constantly. As the miniaturization of the gate length leads to the approximation of two charge storage units located on the left and right in the same memory cell, a severe second bit effect then occurs and easily results in erroneous reading. In addition, since the source region and the drain region are miniaturized, the source region and the drain region fail to block the secondary hot electrons generated when the selected memory cell is programmed. The second hot electrode is thus injected into the adjacent memory cell to generate program disturbance and thereby lowering the reliability of memory device.